Echelon Neuron Manuel d'utilisateur

078-0399-01BDevelop assembly language functions using the Neuron® Assembly Language.Neuron Assembly Language Reference Guide

_sub16s (Subtract Signed, 16 Bit) ... 193 _xor16 (Exclusive OR, 16 Bit) ...

MUL (Multiply) The MUL instruction performs integer multiplication. The MUL instruction uses the implicit addressing mode. The instruct

NOP (No Operation) The NOP instruction performs no operation. The NOP instruction uses the implicit addressing mode. This instruction is a one-byt

NOT (Not) The NOT instruction performs a logical NOT operation on the value in TOS. The NOT instruction uses the implicit addressing mode. This ins

OR (Or) The OR instruction performs a logical OR for two numbers. The OR instruction uses one of two addressing modes: • In implicit addressing mo

OR_R (Or and Return) The OR_R instruction performs a logical OR for two numbers and performs a return-from-call operation. The OR_R instruction uses

POP (Pop from Stack) The POP instruction pops a value from the data stack to a specified location. The POP instruction uses one of the following ad

POP [2][offset] POP [3][offset] POP [0][TOS] POP [1][TOS] POP [2][TOS] POP [3][TOS] POP FLAGS POP RS

Instruction Hexadecimal Opcode Instruction Size (Bytes) CPU Cycles Required Affect on Carry Flag POP [3][offset] DB 2 7 None POP [0][TOS] DC 1

Instruction Hexadecimal Opcode Instruction Size (Bytes) CPU Cycles Required Affect on Carry Flag POP !15 CF 1 4 None POP !16 D0 1 4 None POP

xch ; ( n, 0 ) pop !tos ; ( n ) drop_r tos ; return to caller Neuron Assembly Language

1 Introduction This chapter introduces the Neuron assembly language and the Neuron Assembler. Neuron Assembly Language Reference 1

POPD (Pop Pointer Direct) The POPD instruction pops the two bytes from TOS and NEXT on the data stack into the specified pointer register. The POPD

POPPUSH (Pop from Data Stack and Push onto Return Stack) The POPPUSH instruction pops TOS from the data stack and pushes the value onto the return s

PUSH (Push onto Stack) The PUSH instructions push a value from a specified location onto the data stack. The PUSH instruction uses one of the follow

base page register (BP) into NEXT on the data stack. This instruction modifies NEXT but preserves TOS. The PUSH instruction applies to Series 3100,

PUSH [RSP] PUSH !TOS The number sign or hash (#) is required to specify the immediate value for the PUSH #number instruction. The e

Instruction Hexadecimal Opcode Instruction Size (Bytes) CPU Cycles Required Affect on Carry Flag PUSH address B7 3 7 None PUSH TOS A4 1 3 No

Examples: The following example assumes that the stack contains two 16-bit elements, A and B, with A nearest to the top of the stack. The example pla

PUSHD (Push Pointer Direct) The PUSHD instruction pushes two bytes from the specified location into TOS and NEXT on the data stack. The PUSHD instr

Instruction Hexadecimal Opcode Instruction Size (Bytes) CPU Cycles Required Affect on Carry Flag PUSHD [3] B3 1 6 None PUSHD #expression B5 3 6

PUSHPOP (Pop from Return Stack and Push onto Data Stack) The PUSHPOP instruction pops the byte from the top of the return stack and pushes it into T

Introduction An application program for a LONWORKS device that runs on a Series 3100, Series 5000, or Series 6000 Neuron Chip or Smart Transceiver use

PUSHS (Push Short) The PUSHS instruction pushes the value of the specified operand number into TOS. The PUSHS instruction uses the immediate address

RET (Return from Call) The RET instruction performs a return-from-call operation. The RET instruction uses the implicit addressing mode. The RET in

ROLC (Rotate Left through Carry) The ROLC instruction rotates the byte in TOS one bit to the left, using the Carry flag as an input bit. The ROLC

RORC (Rotate Right through Carry) The RORC instruction rotates the byte in TOS one bit to the right, using the Carry flag as an input bit. The RORC

SBC (Subtract with Carry) The SBC instruction subtracts two numbers, and uses the value of the Carry flag as input to the subtrahend. The SBC instru

SBR (Short Branch) The SBR instruction performs an unconditional branch. The SBR instruction uses the (short) relative addressing mode. The SBR in

Instruction Hexadecimal Opcode Instruction Size (Bytes) CPU Cycles Required Affect on Carry Flag SBR *+10 29 1 1 None SBR *+11 2A 1 1 None SB

SBRNZ (Short Branch If Not Zero) The SBRNZ instruction performs a conditional branch if TOS is not zero. The SBRNZ instruction uses the (short) rel

Instruction Hexadecimal Opcode Instruction Size (Bytes) CPU Cycles Required Affect on Carry Flag SBRNZ *+10 69 1 3 None SBRNZ *+11 6A 1 3 Non

SBRZ (Short Branch If Zero) The SBRZ instruction performs a conditional branch if TOS is zero. The SBRZ instruction uses the (short) relative addre

• Chapter 8, System-Provided Functions, describes system-provided functions for various arithmetical or logical operations or for stack management.

Instruction Hexadecimal Opcode Instruction Size (Bytes) CPU Cycles Required Affect on Carry Flag SBRZ *+10 49 1 3 None SBRZ *+11 4A 1 3 None

SHL (Shift Left) The SHL instruction shifts the byte in TOS one bit to the left. The SHL instruction uses the implicit addressing mode. This instr

SHLA (Shift Left Arithmetically) The SHLA instruction shifts the byte in TOS one bit to the left arithmetically. The SHLA instruction uses the impli

SHR (Shift Right) The SHR instruction shifts the byte in TOS one bit to the right. The SHR instruction uses the implicit addressing mode. This ins

SHRA (Shift Right Arithmetically) The SHRA instruction shifts the byte in TOS one bit to the right arithmetically. The SHRA instruction uses the imp

SUB (Subtract) The SUB instruction subtracts two numbers. The SUB instruction uses the direct addressing mode, in two forms, subtract NEXT from TOS

The value of TOS after the first subtraction is 1 because 3-2 = 1. In this case, the value of the Carry flag is cleared because the unsigned subtract

XCH (Exchange) The XCH instruction exchanges the contents of TOS and NEXT on the data stack. The XCH instruction uses the implicit addressing mode.

XOR (Exclusive Or) The XOR instruction performs a logical exclusive OR (XOR) for two numbers. The OR instruction uses one of two addressing modes: •

XOR_R (Exclusive Or and Return) The XOR_R instruction performs a logical exclusive OR (XOR) for two numbers and performs a return-from-call operatio

where –switches define any optional command-line switches (see NAS Command Switches) and file.ns specifies the source input file to assemble. The com

7 Neuron Assembler Directives The Neuron Assembler provides various directives to control the inclusion of additional source files, to control co

Overview of the Assembler Directives An assembler directive provides information to the Neuron Assembler to control or affect the processing of the re

RADIX Specify default numeric base RESOURCE Control resource (compiler generated) The directives have syntax analogous to the assembly instructions

APEXP (Application Symbol Export) The APEXP directive is used to export symbols that interface with the Neuron C application. An exported symbol must

DATA.B (Reserve Initialized Memory) The DATA.B directive is used to reserve memory and initialize the reserved memory to specific values. See also

%lookupTable DATA.B h’12,h’2C,h’39 The following example defines a constant string “Hello, World!” and includes a terminating zero byte:

ELSE (Conditional Assembly) The Neuron assembler provides the following directives for conditional control of the assembly of blocks of source lines

END (Assembly Control) The END directive instructs the Neuron assembler to stop reading the current file and stop compiling. This directive is optio

ENDIF (Conditional Assembly) The Neuron assembler provides the following directives for conditional control of the assembly of blocks of source line

Table 1. Command Switches for the nas Command Command Switch Description Long Form Short Form --autotrunc -a Auto-truncate literals for byte-immedi

EQU (Equate Symbol) The EQU directive assigns the value of a constant expression to a symbol. The assembler treats subsequent occurrences of the sym

ERROR (Conditional Assembly) The ERROR directive causes the Neuron Assembler to display a user-defined error message. This error leads to an assemb

EXPORT (Export Symbol) The EXPORT directive is used to export symbols that interface with other Neuron Assembly modules. An exported symbol must be d

IF (Conditional Assembly) The Neuron assembler provides the following directives for conditional control of the assembly of blocks of source lines:

IFDEF (Conditional Assembly) The Neuron assembler provides the following directives for conditional control of the assembly of blocks of source lines

IFNDEF (Conditional Assembly) The Neuron assembler provides the following directives for conditional control of the assembly of blocks of source lin

IMPORT (Import External Symbol) The IMPORT directive is used to import symbols from other Neuron Assembly modules or a Neuron C application. An impor

INCLUDE (Assembly Control) The INCLUDE directive is used to include additional assembly source-code modules in the compilation of the current file.

LIBRARY (Include Library) The LIBRARY directive is used to instruct the linker to use a specific function library when linking an application conta

Example: The following example advises the Neuron Linker to include the Echelon provided CENELEC library when linking an application that uses the cu

The Neuron Librarian, available from the command line as NLIB.EXE, allows you to create and manage libraries, or add and remove individual object file

LIST (Listing Control) The LIST and NOLIST directives control whether assembly source statements are included in a listing file (produced by specifyi

NOLIST (Listing Control) The LIST and NOLIST directives control whether assembly source statements are included in a listing file (produced by speci

ORG (Segment Control) The ORG directive closes the currently open and active segment, and opens a new segment of the same type. When a segment is cl

PAGE (Listing Control) The PAGE directive begins a new page in an assembly listing file (produced by specifying the --listing keyword on the command

RADIX (Default Radix) The RADIX directive sets the default radix (numeric base) used for constant numeric expressions until another RADIX directive i

RES (Reserve Uninitialized Memory) The RES directive reserves a block of memory for uninitialized data. See also DATA.B (Reserve Initialized Memor

RESOURCE (Resource Control) The RESOURCE directive is used by the Neuron C compiler to specify various preferences and requirements to its companion

SEG (Segment Control) The SEG directive controls the currently open segment type. Any of the supported segment types (including the one that is cur

SUBHEAD (Listing Control) The SUBHEAD directive specifies the text for the subheading line of the assembly listing file (produced by specifying the -

8 System-Provided Functions This chapter describes the system-provided functions that are used by the Neuron C compiler. Neuron Assembly Language

recommended. If no file name extension is provided on the command line, the Neuron Assembler assumes an .ns extension. A file that is used with the

Overview of the Functions The Neuron firmware provides certain functions for common programming tasks that can make Neuron assembly language programmi

_abs8 (Absolute Value, 8 Bit) This function returns the absolute value of a signed integer. Stack Transformation: (a -- |a|) Location: Near Regist

_add_8_16f (Add Fast, 8 Bit to 16 Bit) This function adds an 8-bit value to a 16-bit value. The “f” stands for “fast” in that if there is no carry, o

This example causes 13 bytes of zeroes to be pushed onto the data stack. push #d’13 ; (13) call _alloc ; (0(13)) _

Stack Transformation: (value(2) -- value(2)-1) Location: Near Registers Affected: None Example: This example decrements 300. pushd #d’300

_div8 (Divide, 8 Bit) This function divides two integers to produce an integer result. The result of dividing by zero is zero and a software error i

call _drop_n ; () _drop_n_preserve_1 (Drop N Bytes from Stack and Preserve NEXT) This function preserves NEXT and removes the next N i

Example: This example drops 3 bytes from the stack and returns to the caller of LocalFunction. callr LocalFunction ; (a, b, c, d) ;

call _equal16 ; (0) _equal8 (Equality Test, 8 Bit) This function returns true if two 8-bit values are equal. The native XOR instructio

Example: This example determines if d’10 >= d’20. push #d’20 ; (d’20) push #d’10 ; (d’10, d’20) call

The object output file contains assembled code, ready for the Neuron Linker. Typically, the object output file has the same name as the input source

Registers Affected: None Example: This example increments 300. pushd #d’300 ; (44, 1) call _inc16 ; (45, 1) io_iacc

watchdog timer reset. A Neuron C application can use the #pragma deadlock_is_infinite compiler directive to avoid the watchdog timer reset. Do not

This example acquires the semaphore, then modifies a global variable, then releases the semaphore. import io_iaccess, io_irelease

Registers Affected: None Example: This example shifts 16 left 2. pushs #d’2 ; (d’2) push #d’16 ; (d’16, d’2)

Location: Near Registers Affected: P0 is modified and contains address(2) Example: This example loads two bytes from address h’f000, which for this

Stack Transformation: (a, b -- a<b) Location: Near Registers Affected: None Example: This example determines if d’10 < d’20. push

Stack Transformation: (a – a?1:0) Location: Near Registers Affected: None Example: This example returns the logical value for 5. pushs #

_lshift16_add16 (Left Shift and Add, 16 Bit) This function takes a 16-bit index, shifts it left n times, and adds the result to a base value. Stack

Registers Affected: None Example: This example uses a base of h’efe3 and an index of 10. pushd #h’efe3 ; (h’e3, h’ef)

Stack Transformation: (a(2), b(2) -- max(a(2),b(2))) Location: Near Registers Affected: None Example: This example gets the maximum of -8 and 2.

• label is an optional identifier, followed by white space • keyword is a reserved name for an assembly instruction or Assembler directive • The

_memcpy (Copy Memory) This function performs the equivalent of a memcpy() function for a non-zero amount of data. len cannot be 0. Also, _memcpy doe

Example: This example initializes four bytes at h’eff0 to 33. pushs #d’4 ; (d’4) push #d’33 ; (d’33, d’4)

Location: Near Registers Affected: None Example: This example gets the minimum of -8 and 2. pushd #d’2 ; (d’2, 0) pushd

Stack Transformation: (a(2) -- -a(2)) Location: Near Registers Affected: None Example: This example negates 2. pushd #d’2 ; (d’

Stack Transformation: (a(2), b(2) -- a(2)*b(2)) Location: Near Registers Affected: R0, P0, P3 Example: This example multiplies 50 times 40.

_mul8s (Multiply Signed, 8 Bit) This function multiplies two signed integers to produce an integer result. Stack Transformation: (a, b -- a*b) Loca

push #d’40 ; (d’40, d’50, 0) call _muls_8_16 ; (d’208, 7) _mul8l (Multiply, 8 Bit with 16 Bit Result) This function mul

pushd #d’8 ; (d’8, 0) call _not16 ; (d’247, d’255) _or16 (Or, 16 Bit) This function returns the bitwise OR of two

Example: This example does the equivalent of a POP [DSP][-9]. ; (a, b, c, d, …, h, i, j, k) pushs #7

_push (Push from Offset to TOS) This function is used to fetch a location from the stack. It can be thought of as an extension to the instruction PU

Echelon, LONWORKS, LONMARK, NodeBuilder, LonTalk, Neuron, 3120, 3150, ShortStack, LonMaker, and the Echelon logo are trademarks of Echelon Corporation

See Chapter 6, Neuron Assembly Language Instruction Statements, for a description of all supported instructions. Operands Many Neuron assembly instruc

Example: ; (a, b, c, d) call _push4 ; (a, b, c, d, a, b, c ,d) _pushd (Push from Offset to TOS and NEXT,

Stack Transformation: (a(2), b -- a(2)>>b) Location: Near Registers Affected: None Example: This example shifts 16 right 2. pushs

Stack Transformation: (a -- a>>n) Location: Near Registers Affected: None Example: This example shifts 16 right 3. push #d’16

_sign_extend16 (Convert 8 Bit to 16 Bit, Preserve Sign) This function sign extends an 8-bit value. If the most-significant byte (MSB) of the value i

pushd #d’50 ; (d’50, 0, d’44, 1) call _sub16s ; (d’250, 0) _xor16 (Exclusive OR, 16 Bit) This function returns the bi

A Neuron Assembly Instructions Listed by Mnemonic This appendix lists the Neuron assembly instructions by mnemonic. Neuron Assembly Language Refere

Instructions by Mnemonic Table 62 lists the Neuron assembly language instructions, ordered by mnemonic. The table also summarizes the operation perfo

Mnemonic Operand Operation Description ALLOC #literal [DSP+1] = TOS DSP = DSP + literal IP = IP+1 Move DSP by literal. Literal range is 1 to 8.

Mnemonic Operand Operation Description BRZ label IF [TOS]=0 IP = IP+SD TOS = [DSP--] IP = IP+2 Drop TOS, branch if TOS was zero. The IP-rela

Mnemonic Operand Operation Description DIV TEMP = int([DSP] ÷ TOS) TOS = int([DSP] % TOS) [DSP] = TEMP IP++ Divide unsigned integer in NEXT by

Symbols A symbol is one or more consecutive alphanumeric characters. A symbol can comprise either lower or upper case letters a..z or A..Z, the digi

Mnemonic Operand Operation Description NOP IP = IP + 1 No operation is done. NOT TOS = NOT TOS C = 0 IP = IP+1 Change TOS to its one's

Mnemonic Operand Operation Description POP [DSP][D] [BP + DSP + D]= TOS TOS = [DSP--] IP = IP+1 Pop DSP relative with displacement D. Negative

Mnemonic Operand Operation Description PUSH [PTR] [D] [++DSP] = TOS TOS = [[BP+(PTR*2)]+D] IP = IP+2 Pushes 8-bit value at address held in 2-byte

Mnemonic Operand Operation Description ROLC C = TOS MSB TOS = TOS << 1 TOS LSB = OLD C IP = IP+1 Rotate TOS left through CARRY by one. RO

Mnemonic Operand Operation Description SHL TOS = TOS <<1 TOS LSB = 0 C = 0 IP = IP+1 Logical shift TOS left by one. SHLA C = TOS MSB T

Mnemonic Operand Operation Description XOR TOS = TOS ^ [DSP--] C = 0 IP = IP+1 Bitwise XOR of TOS and NEXT. Drop NEXT. XOR #literal TOS =

B Neuron Assembly Instructions Listed by Hexadecimal Opcode This appendix lists the Neuron assembly instructions by opcode. Neuron Assembly Languag

Instructions by Opcode Table 63 lists the Neuron assembly language instructions, ordered by hexadecimal opcode. The table also summarizes the number

Hexadecimal OpCode Mnemonic Number of Operands Instruction Size Number of Cycles 13 CALL 1 2 6 14 CALL 1 2 6 15 CALL 1 2 6 16 CALL 1

Table 2. Unary Operators Operator Description - Two’s-complement arithmetic negation ~ One’s-complement bitwise negation Binary operators are symb

Hexadecimal OpCode Mnemonic Number of Operands Instruction Size Number of Cycles 2B SBR 0 1 1 2C SBR 0 1 1 2D SBR 0 1 1 2E SBR 0 1 1

Hexadecimal OpCode Mnemonic Number of Operands Instruction Size Number of Cycles 43 SBRZ 0 1 3 44 SBRZ 0 1 3 45 SBRZ 0 1 3 46 SBRZ 0

Hexadecimal OpCode Mnemonic Number of Operands Instruction Size Number of Cycles 5B XOR #number 1 2 3 5C ADD_R 0 1 7 5D AND_R 0 1 7 5E O

Hexadecimal OpCode Mnemonic Number of Operands Instruction Size Number of Cycles 73 BRZ 1 2 4 74 CALLR 1 2 5 75 BRF 2 3 4 76 BRNEQ 2

Hexadecimal OpCode Mnemonic Number of Operands Instruction Size Number of Cycles 8B PUSH !11 0 1 4 8C PUSH !12 0 1 4 8D PUSH !13 0 1 4 8E

Hexadecimal OpCode Mnemonic Number of Operands Instruction Size Number of Cycles A3 PUSH DSP 0 1 4 A4 PUSH TOS 0 1 3 A5 PUSH NEXT 0 1 4

Hexadecimal OpCode Mnemonic Number of Operands Instruction Size Number of Cycles BB PUSH DSP[-5] 0 1 5 BC PUSH DSP[-4] 0 1 5 BD PUSH DSP[-3]

Hexadecimal OpCode Mnemonic Number of Operands Instruction Size Number of Cycles D3 POP !19 0 1 4 D4 POP !20 0 1 4 D5 POP !21 0 1 4 D6

Hexadecimal OpCode Mnemonic Number of Operands Instruction Size Number of Cycles EB - - - - EC MUL 0 1 14 ED DIV 0 1 14 EE - - - - EF

C Reserved Keywords This appendix lists the keywords that are reserved to the Neuron Assembler or the Neuron C compiler. Neuron Assembly Language

Table 5. Special Operator Functions Function Description LB Extracts the low byte of the expression HB Extracts the high byte of the expression (l

Keywords Table 64 lists the reserved keywords for the Neuron Assembler or the Neuron C compiler. Not all of the keywords are available to the program

Index # #pragma include_assembly_file, 39, 42 _ _abs16 function, 160 _abs8 function, 161 _add_8_16 function, 162 _add_8_16f function, 162 _add16 func

add16s function, 161 address expression, 14 addressing mode absolute, 30 BP indexed, 33 BP relative, 32 direct, 30 DSP relative, 32 immediate, 30 impl

EXPORT directive, 142 expression address, 14 constant, 13 general, 11 F file format, 7 naming convention, 6 output, 7 source, 6 FLAGS register, 21 fo

gequ8s function, 169 get_sp function, 169 global data, 29 H hardware resources, 17 I IF directive, 143 IFDEF directive, 144 IFNDEF directive, 145 imme

M max16 function, 178 max16s function, 178 max8 function, 179 max8s function, 179 memcpy function, 179 memcpy1 function, 180 memory map, 26 memset fu

SEG directive, 157 segment, 25 SHL instruction, 121 SHLA instruction, 122 SHR instruction, 123 SHRA instruction, 124 sign_extend16 function, 192 speci

Displacements A displacement is a relative address value. A displacement can be interpreted as a signed or unsigned number, depending on the instruct

2 Neuron Architecture for Neuron Assembly Programming This chapter describes elements of the Neuron architecture that apply to writing a function i

Neuron Architecture For Series 3100 devices, the architecture of a Neuron Chip or Smart Transceiver includes three independent processors that share a

A Neuron Chip or Smart Transceiver is a big-endian device, that is, the most-significant byte (MSB) of an address or a 16-bit scalar is at a lower me

General-Purpose Registers The Neuron architecture defines 16 hardware memory locations that the Neuron Assembler uses as general-purpose registers, ty

A scratch register is one that can be used for temporary data storage by multiple programs or functions. Although some operations support a special

Welcome Echelon’s Neuron® assembly language is the symbolic programming language for Series 3100, Series 5000, and Series 6000 Neuron Chips and Smart

Table 7. Pointer Registers Pointer Register Description P0 Scratch register. A function can use this register as needed. Assume that any call to t

P0 EQU 0 P1 EQU 1 P2 EQU 2 P3 EQU 3 Finally, note that the mnemonics are user-defined symbols. Unlike pre-defined re

...lsb(ret)msb(ret)NEXT...GPR0x00000xFFFFBPDSP+RSP+TOSDSP -1DSP -8-1..-8+(DSP-relative addressing mode) 256 Bytes msb P0lsb P0msb P1lsb P1lsb P3R0R1R1

DSP TOS 1 2 3 4 5 Low High NEXT Figure 3. The Data Stack after a Push For two-byte quantities, a two-byte push places the most-significant byte (MSB)

RSP = old RSP - 2HighLow2501??Address of next sequential instruction after call Figure 4. The Return Stack Stack Manipulation The Neuron assembly lan

• POPPUSH to remove the TOS element of the data stack and place it onto the top of the return stack • DROP [RSP] to drop the top of the return stac

Segment Name Usage INITDATA For initialization data. Used by the Neuron C compiler. RAMCODE For code and constant data that resides in off-chip RAM

For the Neuron 3150 Chip and the FT 3150 Smart Transceiver, off-chip memory on these chips consists of one or more of ROM, RAM, EEPROM, NVRAM, or fla

ReservedMandatory EEPROMOn-Chip RAMExtended Memory(Configurable as: Extended RAM or Non-volatile memory)On-Chip ROM0x0000 to 0x3FFF0x4000 to 0xE7FF0xE

Figure 7. Memory Maps for Neuron Chips without Off-Chip Memory Chips with Auto-tuned Memory Series 6000 Neuron Chips and Smart Transceivers support

• Introduction to the LONWORKS Platform (078-0391-01A). This manual provides an introduction to the ISO/IEC 14908 (ANSI/CEA-709.1 and EN14908) Contr

Instead of relying on the developer to specify these memory areas, the Neuron Linker automatically determines the amount of memory required for each t

Direct In the direct addressing mode, the instruction operand is a register name or an expression that resolves to a name of a register. In contrast

Example: push [P0][12] ; ( ) pop [P3][4] ; ([P3][4], ...) The push [P0][12] instruction pushes th

BP Relative In the BP-relative addressing mode, the instruction argument is a general-purpose register (R0 to R15). The register name is prefixed by

instruction pointer IP. Some instructions that use relative addressing support signed distances (that is, support branching in both directions), whil

3 Writing a Neuron Assembly Utility Function This chapter describes general guidelines for writing a utility function in Neuron assembly language.

Overview of Stack-Oriented Programming Neuron assembly language is a stack-oriented programming language, which means that the data stack is the prima

more compact code; see PUSHS (Push Short) for a description of the PUSHS instruction. Note that the stacks and all data registers are 8 bits wide. O

• For the value pi (π), you can use the following approximation: 355/113 (3.1415929203…), which has an error relative to pi of 8.5 * 10-8. • To mul

pushd [SCRATCH16] ; (r(2), piDiv(2)) pushd [SCRATCH16] ; (r(2), r(2), piDiv(2)) ; push the “second half” of pi: pushd #PIFACT

Table of Contents Welcome ... iii Audience ...

the device’s hardware template), the interrupts run on the application processor, and share stacks and common registers with the Neuron C application.

Stack-Effect Comments In general, the data stack is documented as a set of ordered values from left to right, with TOS in the first (left-most) posit

the code element might still be on the stack (if the equality test fails), or might no longer be on the stack (if the equality test succeeds):

Neuron C compiler to copy the contents of a Neuron assembly file as-is into the assembly-language output for the program, as shown in Figure 8. Compi

Copyright (c) Echelon Corporation 1992-2009 0 warning(s), 0 error(s) The --listing option causes the Assembler to generate a listing file. The Neuro

} In addition, you can add a callback function to the test application, and modify the assembly source to call the Neuron C callback function. This

4 Interfacing with a Neuron C Application This chapter describes the conventions and interface requirements for a Neuron assembly function to w

Overview Typically, you use Neuron assembly language to create utilities that can be used with an application that is written in Neuron C. The Neuron

In typical C-language implementations of such functions, the caller is responsible for removing the arguments from the stack after the function compl

Implicit ... 31 Pointer Direct...

This optimization is leads to more efficient code (as the called function might consume its arguments rather than working on copies), and leads to mor

also supports a string format, but does not automatically include the terminating zero-byte. An alternative declaration would have been _%MYDEVICE

Arrays The Neuron Chip and Smart Transceiver hardware has no data alignment requirement, beyond the natural byte alignment. Thus, arrays are consecut

4. Call the function. 5. Process optional function results and clear the stack frame. 6. Restore general-purpose registers saved. Example: The fo

next instructions, but this alternative implementation would use one more byte of code. In this example, it is assumed that the value for the remainin

5 Exploring an Example Function in Neuron Assembly This chapter describes an example function written in Neuron assembly language. This example

Overview of the Checksum Example The checksum example function described in this chapter demonstrates the process of writing and testing a function i

value formerly held in NEXT. Using this instruction prepares for the loop construct that follows. • The POPD instruction takes two bytes from the s

#pragma num_alias_table_entries 0 #pragma include_assembly_file “checksum.ns” extern unsigned Checksum(unsigned, const char*); void TestCall(void) {

6 Neuron Assembly Language Instruction Statements This chapter describes the Neuron assembly language instruction statements that are supported b

BRNC (Branch If Not Carry) ... 73 BRNEQ (Branch If Not Equal) ...

Overview of the Assembly Language Instructions The Neuron assembly language provides instruction statements that control the functionality of the func

Shift and Rotate Operations ROLC Rotate left through carry RORC Rotate right through carry SHL Shift left SHLA Shift left arithmetically SHR Shi

BRZ Branch if zero DBRNZ Decrement and branch if not zero SBRNZ Short branch if not zero SBRZ Short branch if zero Unconditional Program Control O

program memory. The size includes both the opcode and the instruction’s data, if any. • The number of CPU cycles required to execute the instructio

ADC (Add with Carry) The ADC instruction adds two numbers with the value of the Carry flag. The ADC instruction uses the implicit addressing mode.

ADD (Add) The ADD instruction adds two numbers. The ADD instruction uses one of two addressing modes: • In implicit addressing mode, the ADD instr

ADD_R (Add and Return) The ADD_R instruction adds two numbers and performs a return-from-call operation. The ADD_R instruction uses the implicit add

ALLOC (Allocate) The ALLOC instruction allocates a specified number of bytes on the data stack. The specified number of bytes must be in the range

AND (And) The AND instruction performs a logical AND for two numbers. The AND instruction uses one of two addressing modes: • In implicit addressi

AND_R (And and Return) The AND_R instruction performs a logical AND for two numbers and performs a return-from-call operation. The AND_R instructio

IFNDEF (Conditional Assembly) ... 145 IMPORT (Import External Symbol) ...

BR (Branch) The BR instruction performs an unconditional branch. The BR instruction uses the relative addressing mode. The BR instruction branches

BRC (Branch If Carry) The BRC instruction performs a conditional branch if the Carry flag is set. The BRC instruction uses the relative addressing

BRF (Branch Far) The BRF instruction performs an unconditional branch. The BRF instruction uses the relative addressing mode. The

BRNC (Branch If Not Carry) The BRNC instruction performs a conditional branch if the Carry flag is not set. The BRNC instruction uses the relative

BRNEQ (Branch If Not Equal) The BRNEQ instruction compares TOS with a specified number and performs a conditional branch if they are not equal. The

testA brneq #d’65,testB ; ({argument}) callr do_a ; ( ) br exit testB brneq #d’66,testC ; ({argument})

BRNZ (Branch If Not Zero) The BRNZ instruction performs a conditional branch if TOS is not zero. The BRNZ instruction uses one of two addressing mod

BRZ (Branch If Zero) The BRZ instruction performs a conditional branch if TOS is zero. The BRZ instruction uses the relative addressing mode. The

CALL (Call Near) The CALL instruction calls a function at the specified near address. The CALL instruction uses the (short) absolute addressing mode

CALLF (Call Far) The CALLF instruction calls a function at the specified absolute address. The CALLF instruction uses the a

_less16s (Less Than Signed, 16 Bit) ... 174 _less8 (Less Than, 8 Bit) ...

CALLR (Call Relative) The CALLR instruction calls a function at the specified forward or backward signed relative displacement of -126 to +129 bytes.

DBRNZ (Decrement and Branch If Not Zero) The DBRNZ instruction performs two functions: it decrements the unsigned 8-bit value on the t

DEALLOC (Deallocate and Return) The DEALLOC instruction deallocates a specified number of bytes from the data stack, and performs a return from call

myFunction alloc #2 ; ((2)) ... ; function body dealloc #2 ; ( -- ) Neuron Assembly La

DEC (Decrement) The DEC instruction decrements the TOS value. The DEC instruction uses the implicit addressing mode. If the TOS value is zero prio

DIV (Divide) The DIV instruction performs integer division. The DIV instruction uses the implicit addressing mode. The instruction divid

DROP (Drop from Stack) The DROP instruction drops a value from one of the stacks: • The DROP [RSP] instruction drops the top of the return stack •

DROP_R (Drop from Stack and Return) The DROP_R instructions drop a value from the data stack and perform a return from call operation: • The DROP

INC (Increment) The INC instruction can increment the TOS value or the value of a specified pointer register. The INC instruction uses the pointer

Done ... ret ; return to caller Neuron Assembly Language Reference 89